Patent · US Active

Methods for fabricating FinFET structures having different channel lengths

US7960287B2 · kind B2 · utility

22Cited by
3References
9Claims
0Family size

Assignee

Inventors

Key dates

Filing dateSep 27, 2010
Grant dateJun 14, 2011
Priority date
Expiry dateSep 27, 2030

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D30/0245

Abstract

Methods for fabricating FinFET structures having gate structures of different gate widths are provided. The methods include the formation of sidewall spacers of different thicknesses to define gate structures of the FinFET structures with different gate widths. The width of a sidewall spacer is defined by the height of the structure about which the sidewall spacer is formed, the thickness of the sidewall spacer material layer from which the spacer is formed, and the etch parameters used to etch the sidewall spacer material layer. By forming structures of varying height, forming the sidewall spacer material layer of varying thickness, or a combination of these, sidewall spacers of varying width can be fabricated and subsequently used as an etch mask so that gate structures of varying widths can be formed simultaneously.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.