Patent · US Active

Fast evaluation of average critical area for IC layouts

US7962882B2 · kind B2 · utility

1Cited by

5References

14Claims

0Family size

Assignee

SYNOPSYS, INC. · US

Inventors

Qing Su · Sunnyvale, US
Subarnarekha Sinha · Menlo Park, US
Charles C. Chiang · San Jose, US

Key dates

Filing date	Feb 15, 2008
Grant date	Jun 14, 2011
Priority date	—
Expiry date	Oct 22, 2029

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/39
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Method and apparatus for approximating the average critical area of a layout or layout region, involving summing, over all the object segments of interest, respective critical area contribution values that are dependent upon particular layout parameters of the objects, each of the contribution values being representative of a plurality of defect sizes, and being defined such that for each defect size in the plurality of defect sizes, and for a particular defect type, the contribution values collectively count all critical areas arising due to the object segments of interest only once.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.