Chip stack, chip stack package, and method of forming chip stack and chip stack package
US7964948B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 25, 2007 |
| Grant date | Jun 21, 2011 |
| Priority date | — |
| Expiry date | Feb 10, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip stack may include a first chip and a second chip stacked on the first chip. Each of the first and second chips may include a substrate having an active surface and an inactive surface opposite to the active surface; an internal circuit in the active surface; an I/O chip pad on the active surface and connected to the internal circuit through an I/O buffer; and a I/O connection pad connected to the I/O chip pad through the I/O buffer by a circuit wiring. A redistributed I/O chip pad layer may be on the active surface of the first chip, the redistributed I/O chip pad layer redistributing the I/O chip pad. The I/O connection pads of the first chip and the second chip may be electrically connected to each other by an electrical connecting part.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.