Semiconductor with through-substrate interconnect
US7968460B2 · kind B2 · utility
36Cited by
9References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 19, 2008 |
| Grant date | Jun 28, 2011 |
| Priority date | — |
| Expiry date | Jul 13, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/101
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer. Method of fabricating the semiconductor device can include etching a via into a semiconductor substrate, filling the via with a metal material, forming a metal routing layer subsequent to filling the via, and removing a portion of a bottom of the semiconductor substrate to expose a bottom region of the metal filled via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.