Memory architecture having a reference current generator that provides two reference currents

US7969804B1 · kind B1 · utility

Assignee

• Cypress Semiconductor Corporation · US

Inventors

• Ryan T. Hirose · Colorado Springs, US
• Fredrick B. Jenne · Tracy, US
• Vijay Srinivasaraghavan · Colorado Springs, US
• Igor G. Kouznetsov · San Jose, US
• Paul Fredrick Ruths · Woodland Park, US
• Cristinel Zonte · Colorado Springs, US
• Bogdan I. Georgescu · Colorado Springs, US
• Leonard Vasile Gitlan · Colorado Springs, US
• James Paul Myers · Miami, US

Key dates

• Filing date: Dec 24, 2008
• Grant date: Jun 28, 2011
• Expiry date: Feb 4, 2029

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C16/32
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A memory architecture is provided with an array of non-volatile memory cells arranged in rows and columns, and a sense amplifier coupled to at least one column within the array for sensing a data bit stored within one of the non-volatile memory cells. In order to provide accurate sensing, a reference current generator is provided and coupled to the sense amplifier. The reference current generator provides a first reference current having adjustable magnitude and adjustable slope, and a second reference current having adjustable magnitude, but constant slope. The first reference current is supplied to the sense amplifier for sensing the data bit. The second reference current is supplied to a control block for generating clock signals used to control sense amplifier timing.