Method and system for electromigration analysis on signal wiring
US7971171B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 20, 2008 |
| Grant date | Jun 28, 2011 |
| Priority date | — |
| Expiry date | Aug 25, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention relates to an electromigration analysis method and a system for analyzing one or more nets in a digital integrated circuit design that are at risk of electromigration. The method comprises the steps of providing at least one interconnect between a driver cell and at least one load cell; applying same extracted netlist data for noise and/or timing analysis and for electromigration analysis; modeling the driver cell by a train of trapezoidal voltage pulses transmitted from the driver cell to the one or more load cells through the at least one interconnect; extracting at least a slew rate of a driver voltage signal and/or timing information from a noise and/or timing analysis for the one or more nets; and comparing a locally measured current density in the at least one interconnect to an effective local maximum current density limit of the at least one interconnect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.