Method of forming a field effect transistors with a sacrificial stressor layer and strained source and drain regions formed in recesses

US7972916B1 · kind B1 · utility

Assignee

• ACORN TECHNOLOGIES, INC. · US

Inventors

• Daniel J. Connelly · San Francisco, US
• Paul A. Clifton · Santa Monica, US
• R. Stockton Gaines · Santa Monica, US

Key dates

• Filing date: Oct 22, 2008
• Grant date: Jul 5, 2011
• Expiry date: Jan 30, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/797

Abstract

The process forms a FET with a channel region that has in plane compressive stress in one direction and in plane tensile stress in a perpendicular direction. The process deposits a germanium silicon sacrificial stressor layer on a silicon substrate so that the germanium silicon is in a state of compressive stress. Etching trenches forms silicon pillars covered by the stressor layer and transfers tensile strain to the upper portion of the pillar. The process fills the trenches with stiff insulating material to maintain the strain in the pillar and etching removes the stressor layer. More etching creates recesses on either side of a channel region in the upper portion of the pillar. Doped germanium silicon layers fill the recesses, apply lateral compressive stress to the pillar's channel region and act as source and drain electrodes. A gate is formed above the strained channel region.