Polished semiconductor wafer and process for producing it

US7972963B2 · kind B2 · utility

Assignee

• Siltronic AG · DE

Inventors

• Thomas Teuschler · Burghausen, DE
• Guenter Schwab · Vilshofen an der Donau, DE
• Maximilian Stadler · Haiming, DE

Key dates

• Filing date: Oct 11, 2007
• Grant date: Jul 5, 2011
• Expiry date: Feb 6, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/6708
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A polished semiconductor wafer has a front surface and a back surface and an edge R, which is located at a distance of a radius from a center of the semiconductor wafer, forms a periphery of the semiconductor wafer and is part of a profiled boundary of the semiconductor wafer. The maximum deviation of the flatness of the back surface from an ideal plane in a range between R-6 mm and R-1 mm of the back surface is 0.7 μm or less. A process for producing the semiconductor wafer, comprises at least one treatment of the semiconductor wafer with a liquid etchant and at least one polishing of at least a front surface of the semiconductor wafer, the etchant flowing onto a boundary of the semiconductor wafer during the treatment, and the boundary of the semiconductor wafer which faces the flow of etchant being at least partially shielded from being struck directly by the etchant. The shielding extends in the direction of a thickness d of the semiconductor wafer and is at least d+100 μm long.