Integrated RF ESD protection for high frequency circuits
US7973365B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 25, 2008 |
| Grant date | Jul 5, 2011 |
| Priority date | — |
| Expiry date | Oct 5, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention relates to a high-frequency integrated circuit requiring ESD protection for a circuit node. One or more metallic layer is deposited within the integrated circuit and patterned to form a transmission line. The metallic layers are generally already present in the integrated circuit for signal routing. The transmission line is coupled between the circuit node and a terminal of an ESD protection device, with a transmission line return conductor coupled to a high-frequency ground. The transmission line is formed with an electrical length that transforms the impedance of the ESD protection device substantially into an open circuit at the circuit node at an operational frequency of the integrated circuit. The other terminal of the ESD protection device is coupled to the high-frequency ground.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.