Methodology for assessing degradation due to radio frequency excitation of transistors
US7974595B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 11, 2008 |
| Grant date | Jul 5, 2011 |
| Priority date | — |
| Expiry date | Dec 11, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3161
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
One embodiment relates to an on-chip power amplifier (PA) test circuit. In one embodiment, a PA test circuit comprises a controllable oscillator (CO) configured to generate a radio frequency (RF) signal, a parallel resonant circuit tuned to the radio frequency, a pre-power amplifier (PPA) coupled to the CO and the parallel resonant circuit, the PPA configured to amplify and drive the RF signal from an output of the PPA into a load. The test circuit may further comprise a first transmission gate configured to couple the RF signal from the CO to an input of the PPA. One testing methodology for a PA test circuit comprises stressing the PPA with an RF signal, measuring a characteristic of the PPA, determining stress degradation from the characteristic measurements, and repeating the stressing and characteristic measurements until a maximum stress degradation is achieved or a maximum stress has been applied.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.