Enhanced cap layer integrity in a high-K metal gate stack by using a hard mask for offset spacer patterning

US7981740B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Markus Lenski · Dresden, DE
• Kerstin Ruttloff · Frankenberg/Sachsen, DE
• Martin Mazur · Pulsnitz, DE
• Frank Seliger · Dresden, DE
• Ralf Otterbach · Dresden, DE

Key dates

• Filing date: Jun 23, 2010
• Grant date: Jul 19, 2011
• Expiry date: Jun 23, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0184

Abstract

When forming transistor elements on the basis of sophisticated high-k metal gate structures, the efficiency of a replacement gate approach may be enhanced by more efficiently adjusting the gate height of transistors of different conductivity type when the dielectric cap layers of transistors may have experienced a different process history and may thus require a subsequent adaptation of the final cap layer thickness in one type of the transistors. For this purpose, a hard mask material may be used during a process sequence for forming offset spacer elements in one gate electrode structure while covering another gate electrode structure.