Integrated circuit chip assembly having array of thermally conductive features arranged in aperture of circuit substrate
US7982307B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 22, 2006 |
| Grant date | Jul 19, 2011 |
| Priority date | — |
| Expiry date | Jul 19, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/041
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An assembly comprises a stiffener, a circuit substrate and an IC chip. The stiffener has a surface with a first region and a second region. The circuit substrate covers at least a portion of the first region of the stiffener, while the IC chip overlies at least a portion of each of the first and second regions of the stiffener. The assembly further comprises a signal solder bump and a thermally conductive feature. The signal solder bump contacts the IC chip and the circuit substrate. The thermally conductive feature is disposed between, and is metallurgically bonded to, the integrated circuit chip and the second region of the stiffener. The thermally conductive feature provides an efficient thermal conductivity pathway between the IC chip and the stiffener.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.