Semiconductor device including stress relaxation gaps for enhancing chip package interaction stability

US7982313B2 · kind B2 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Michael Grillberger · Radebeul, DE
• Matthias Lehr · Dresden, DE

Key dates

• Filing date: Jul 22, 2009
• Grant date: Jul 19, 2011
• Expiry date: Jul 22, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/1433
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

By dividing a single chip area into individual sub-areas, a thermally induced stress in each of the sub-areas may be reduced during operation of complex integrated circuits, thereby enhancing the overall reliability of complex metallization systems comprising low-k dielectric materials or ULK material. Consequently, a high number of stacked metallization layers in combination with increased lateral dimensions of the semiconductor chip may be used compared to conventional strategies.