Implementing minimized latency and maximized reliability when data traverses multiple buses
US7984357B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 27, 2007 |
| Grant date | Jul 19, 2011 |
| Priority date | — |
| Expiry date | May 18, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1044
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller and methods implement minimized latency and maximized reliability when data traverses multiple buses. The memory controller includes a dynamic random access memory (DRAM) error correcting code (ECC) checking and correcting circuit and a high speed bus (HSB) ECC checking and correcting circuit. In a first mode for implementing minimized latency, read data is applied directly to the DRAM ECC checking and correcting circuit, bypassing the HSB ECC checking and correcting circuit. In a second mode for implementing maximized reliability, the read data is applied through the HSB ECC checking and correcting circuit to the DRAM ECC checking and correcting circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.