Structures incorporating semiconductor device structures with reduced junction capacitance and drain induced barrier lowering
US7984408B2 · kind B2 · utility
31Cited by
10References
8Claims
0Family size
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Key dates
| Filing date | Oct 19, 2007 |
| Grant date | Jul 19, 2011 |
| Priority date | — |
| Expiry date | Mar 6, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/685
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes semiconductor device structures characterized by reduced junction capacitance and drain induced barrier lowering. The semiconductor device structure of the design structure includes a semiconductor layer and a dielectric layer disposed between the semiconductor layer and the substrate. The dielectric layer includes a first dielectric region with a first dielectric constant and a second dielectric region with a second dielectric constant that is greater than the first dielectric constant.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.