Method and apparatus for making semiconductor packages
US7985621B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2006 |
| Grant date | Jul 26, 2011 |
| Priority date | — |
| Expiry date | Feb 6, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of packaging a plurality of semiconductor chips comprises: providing a substrate panel having a first coefficient of thermal expansion (CTE); providing a carrier having a second CTE that is less than the first CTE; heating the substrate panel and the carrier to first and second elevated temperatures respectively; mounting the substrate panel at about the first elevated temperature to the carrier, the carrier being at said second elevated temperature, to provide a connection between the carrier and the substrate panel; and cooling the carrier and the substrate panel from the first and second elevated temperatures thereby putting the substrate panel into tension in at least one direction. A stiffener panel may be affixed to the substrate panel and heated to an elevated temperature and while the substrate panel is heated to an elevated temperature. A plurality of dies may be mounted and electrically connected to the substrate panel. Under-filling of the plurality of dies may occur with the stiffener panel affixed to the substrate panel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.