Method for manufacturing soi wafer
US7985660B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 16, 2008 |
| Grant date | Jul 26, 2011 |
| Priority date | — |
| Expiry date | Apr 16, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76256
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method for manufacturing an SOI wafer, including: a step of preparing a base wafer consisting of a p+ silicon single crystal wafer and a bond wafer consisting of a silicon single crystal wafer containing a dopant at a lower concentration than that in the base wafer; a step of forming a silicon oxide film on an entire surface of the base wafer based on thermal oxidation; a step of bonding the bond wafer to the base wafer through the silicon oxide film; and a step of reducing a thickness of the bond wafer to form an SOI layer, wherein a step of forming a CVD insulator film on a surface on an opposite side of a bonding surface of the base wafer is provided before the thermal oxidation step for the base wafer. As a result, it is possible to provide the method for manufacturing an SOI wafer which can easily prevent the p-type dopant contained in the base wafer from outwardly diffusing from the surface on the opposite side of the bonding surface of the base wafer due to a high-temperature heat treatment, suppress this dopant from being mixed into the SOI layer, and reduce warpage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.