Method for a gate last process
US7985690B2 · kind B2 · utility
12Cited by
2References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2009 |
| Grant date | Jul 26, 2011 |
| Priority date | — |
| Expiry date | Jun 18, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a semiconductor device is disclosed. The method includes providing a substrate; forming one or more gate structures over the substrate; forming a buffer layer over the substrate, including over the one or more gate structures; forming an etch stop layer over the buffer layer; forming a interlevel dielectric (ILD) layer over the etch stop layer; and removing a portion of the buffer layer, a portion of the etch stop layer, and a portion of the ILD layer over the one or more gate structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.