Floating gate structures

US7989289B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Tejas Krishnamohan · Palo Alto, US
• Krishna K. Parat · Palo Alto, US
• Kyu S. Min · San Jose, US
• Srivardhan Gowda · Boise, US
• Thomas M. Graettinger · Boise, US
• Nirmal Ramaswamy · Boise, US

Key dates

• Filing date: Jun 30, 2008
• Grant date: Aug 2, 2011
• Expiry date: Nov 11, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/035
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Floating gate structures are generally described. In one example, an electronic device includes a semiconductor substrate, a tunnel dielectric coupled with the semiconductor substrate, and a floating gate structure comprising at least a first region having a first electron energy level or electron workfunction or carrier capture efficiency coupled with the tunnel dielectric and a second region having a second electron energy level or electron workfunction or carrier capture efficiency coupled with the first region wherein the first electron energy level or electron workfunction or carrier capture efficiency is less than the second electron energy level or electron workfunction or carrier capture efficiency. Such electronic device may reduce the thickness of the floating gate structure or reduce leakage current through an inter-gate dielectric, or combinations thereof, compared with a floating gate structure that comprises only polysilicon.