Implementing tamper evident and resistant detection through modulation of capacitance
US7989918B2 · kind B2 · utility
10Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 26, 2009 |
| Grant date | Aug 2, 2011 |
| Priority date | — |
| Expiry date | Nov 13, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and tamper detection circuit for implementing tamper and anti-reverse engineering evident detection in a semiconductor chip, and a design structure on which the subject circuit resides are provided. A capacitor is formed with the semiconductor chip including the circuitry to be protected. A change in the capacitor value results responsive to the semiconductor chip being thinned, which is detected and a tamper-detected signal is generated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.