In-memory, in-page directory cache coherency scheme
US7991963B2 · kind B2 · utility
2Cited by
11References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2007 |
| Grant date | Aug 2, 2011 |
| Priority date | — |
| Expiry date | Oct 26, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0817
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an embodiment, the method provides receiving a memory access request for a demanded cache line from a processor of a plurality of processors; accessing coherency information associated with the demanded cache line from a memory unit by bringing in from a memory page in which the demanded cache line is stored, the memory page also including a directory line having coherency information corresponding to the demanded cache line; reading data associated with the demanded cache line in accordance with the coherency information; and returning the data to the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.