Methods and apparatuses for reducing step loads of processors
US7992017B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 11, 2007 |
| Grant date | Aug 2, 2011 |
| Priority date | — |
| Expiry date | Jun 1, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/3203
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatuses for reducing step loads of processors are disclosed. Method embodiments comprise examining a number of instructions to be processed by a processor to determine the types of instructions that it has, calculating power consumption by in an execution period based on the types of instructions, and limiting the execution to a subset of instructions of the number to control the quantity of power for the execution period. Some embodiments may also create artificial activity to provide a minimum power floor for the processor. Apparatus embodiments comprise instruction type determination logic to determine types of instructions in an incoming instruction stream, a power calculator to calculate power consumption associated with processing a number of instructions in an execution period, and instruction throttling logic to control the power consumption by limiting the number of instructions to be processed in the execution period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.