Patent · US Active

Low cost transistors using gate orientation and optimized implants

US7994009B2 · kind B2 · utility

2Cited by

2References

17Claims

0Family size

Inventors

Kamel Benaissa · Garland, US
Greg Baldwin · Plano, US
Shaofeng Yu · Plano, US
Shashank S. Ekbote · San Diego, US

Key dates

Filing date	Jun 26, 2009
Grant date	Aug 9, 2011
Priority date	—
Expiry date	Jan 12, 2030

Classification

Technology area (CPC H)Electricity
CPC primaryH10D84/0135
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

An integrated circuit is disclosed having symmetric and asymmetric MOS transistors of the same polarity, oriented perpendicularly to each other, formed by concurrent halo ion, LDD ion and/or S/D ion implant processes using angled, rotated sub-implants which vary the tilt angle, dose and/or energy between rotations. Implanted halo, LDD and/or S/D source and drain regions formed by angled subimplants may have different extents of overlap with, or lateral separation from, gates of the two types of transistors, producing transistors with two different sets of electrical properties. A process for concurrently fabricating the two types of transistors is also disclosed. Specific embodiments of processes for concurrently forming symmetric and asymmetric transistors are disclosed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.