Patent · US Active

NMOS transistor devices and methods for fabricating same

US7994015B2 · kind B2 · utility

1Cited by

8References

14Claims

0Family size

Assignee

Applied Materials, Inc. · US

Inventors

Sunderraj Thirupapuliyur · San Jose, US
Faran Nouri · Los Altos, US
Yonah Cho · Sunnyvale, US

Key dates

Filing date	Apr 20, 2010
Grant date	Aug 9, 2011
Priority date	—
Expiry date	Apr 20, 2030

Classification

Technology area (CPC H)Electricity
CPC primaryH10D62/822
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

NMOS transistors having controlled channel strain and junction resistance and methods for the fabrication of same are provided herein. In some embodiments, a method for forming an NMOS transistor may include providing a substrate having a p-type silicon region and a gate stack disposed thereon, the gate stack partially defining a source and a drain region; depositing an undoped first silicon layer having a lattice adjusting element atop the p-type silicon region and within the source and the drain regions; and depositing a second silicon layer having a lattice adjusting element and an n-type dopant atop the undoped first silicon layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.