Recessed-gate transistor device having a dielectric layer with multi thicknesses and method of making the same
US7994559B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 2, 2008 |
| Grant date | Aug 9, 2011 |
| Priority date | — |
| Expiry date | Jun 18, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A recessed-gate transistor device includes a gate electrode embedded in a gate trench formed in a semiconductor substrate, wherein the gate trench includes a vertical sidewall and a U-shaped bottom. A source region is provided at one side of the gate trench within the semiconductor substrate. A drain region is provided at the other side thereof. An asymmetric gate dielectric layer is formed between the gate electrode and the semiconductor substrate. The asymmetric gate dielectric layer has a first thickness between the gate electrode and the drain region and a second thickness between the gate electrode and the source region, wherein the first thickness is thicker than the second thickness.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.