Duty cycle corrector and clock generator having the same
US7994834B2 · kind B2 · utility
10Cited by
0References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 30, 2008 |
| Grant date | Aug 9, 2011 |
| Priority date | — |
| Expiry date | May 22, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/017
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A duty cycle corrector includes a delay unit configured to adjust an input clock and an inverted input clock with a delay value controlled in response to one or more control signals and to generate a positive clock and a negative clock, and a duty detector configured to receive the positive clock and the negative clock, to detect duty ratios of the positive clock and the negative clock and to generate the one or more control signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.