DMA engine
US7996581B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 14, 2009 |
| Grant date | Aug 9, 2011 |
| Priority date | — |
| Expiry date | Jan 15, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit and corresponding method for transferring data. The circuit comprises: a CPU; a plurality of addressable devices; and a DMA engine coupled to the CPU and to those devices, the DMA engine comprising a plurality of DMA contexts each having fetch circuitry for fetching a DMA descriptor indicated by the CPU and transfer circuitry for transferring data from one to another of the devices based on a fetched descriptor. The DMA engine further comprises switching means operable to control a group of the contexts to alternate in a complementary sequence between fetching and performing a transfer, such that alternately one or more contexts in the group fetch while one or more others perform a transfer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.