Shared resources in a chip multiprocessor
US7996653B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 7, 2010 |
| Grant date | Aug 9, 2011 |
| Priority date | — |
| Expiry date | Oct 7, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8007
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a node comprises a plurality of processor cores and a node controller configured to receive a first read operation addressing a first register. The node controller is configured to return a first value in response to the first read operation, dependent on which processor core transmitted the first read operation. In another embodiment, the node comprises the processor cores and the node controller. The node controller comprises a queue shared by the processor cores. The processor cores are configured to transmit communications at a maximum rate of one every N clock cycles, where N is an integer equal to a number of the processor cores. In still another embodiment, a node comprises the processor cores and a plurality of fuses shared by the processor cores. In some embodiments, the node components are integrated onto a single integrated circuit chip (e.g. a chip multiprocessor).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.