Patent · US Active

Semiconductor chip with a plurality of scannable storage elements and a method for scanning storage elements on a semiconductor chip

US7996738B2 · kind B2 · utility

5Cited by
6References
20Claims
0Family size

Assignee

Inventors

Key dates

Filing dateMar 5, 2008
Grant dateAug 9, 2011
Priority date
Expiry dateDec 11, 2028

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG01R31/318575
  • WIPO fieldMeasurement
  • WIPO sectorInstruments

Abstract

A semiconductor chip subdivided into power domains, at least one of the power domains is separately activated or deactivated and at least a part of the scannable storage elements are interconnected to one or more scan chains. At least one scan chain is serially subdivided into scan chain portions and the scan chain portion is arranged within one of the power domains. For at least one scan chain portion a bypass line is provided for passing by scan data and at least one select unit is provided for selecting between the bypass line and the corresponding scan chain portion in dependence of the activated or deactivated state of the corresponding power domains.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.