Semiconductor device with isolation trench liner, and related fabrication methods
US7998832B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2008 |
| Grant date | Aug 16, 2011 |
| Priority date | — |
| Expiry date | Jun 23, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76232
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor device is provided herein, where the width effect is reduced in the resulting semiconductor device. The method involves providing a substrate having semiconductor material, forming an isolation trench in the semiconductor material, and lining the isolation trench with a liner material that substantially inhibits formation of high-k material thereon. The lined trench is then filled with an insulating material. Thereafter, a layer of high-k gate material is formed over at least a portion of the insulating material and over at least a portion of the semiconductor material. The liner material divides the layer of high-k gate material, which prevents the migration of oxygen over the active region of the semiconductor material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.