Predicting IC manufacturing yield by considering both systematic and random intra-die process variations
US8000826B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 24, 2006 |
| Grant date | Aug 16, 2011 |
| Priority date | — |
| Expiry date | Nov 16, 2027 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
One embodiment of the present invention provides a system that predicts manufacturing yield for a die within a semiconductor wafer. During operation, the system first receives a physical layout of the die. Next, the system partitions the die into an array of tiles. The system then computes systematic variations for a quality indicative value to describe a process parameter across the array of tiles based on the physical layout of the die. Next, the system applies a random variation for the quality indicative parameter to each tile in the array of tiles. Finally, the system obtains the manufacturing yield for the die based on both the systematic variations and the random variations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.