Synchronization device and methods thereof
US8001409B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 18, 2007 |
| Grant date | Aug 16, 2011 |
| Priority date | — |
| Expiry date | Jun 2, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device includes different clock domains. Each clock domain is synchronized to a different clock signal, and the data transfer between clock domains occurs through a FIFO memory. It is determined which clock domain has a slower clock frequency, and the clock domain associated with the slower clock is selected to generate pointers used to access the FIFO memory in both clock domains. Therefore, the pointers are used to read and write data at the FIFO memory resulting in a transfer of the data between the clock domains. Because the pointers used for data transfer are generated and provided by the clock domain associated with the slower clock, the latency resulting from transferring the pointer between the clock domains is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.