Method and apparatus for compiling programmable logic device configurations
US8001537B1 · kind B1 · utility
1Cited by
18References
25Claims
0Family size
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Key dates
| Filing date | Dec 5, 2005 |
| Grant date | Aug 16, 2011 |
| Priority date | — |
| Expiry date | Apr 10, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/76
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
During compilation of a user logic design in a first type of programmable logic device (e.g., an FPGA), a log is kept of at least certain steps where choices are made. When that logic design is migrated to another type of programmable logic device (e.g., a mask-programmable logic device) the logged steps are taken into account to make sure that the same choices are made, so that the target device is functionally equivalent to the original device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.