Method of integrating stress into a gate stack
US8003503B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 30, 2010 |
| Grant date | Aug 23, 2011 |
| Priority date | — |
| Expiry date | Sep 30, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor device includes providing a dielectric film on a substrate, depositing a metal-containing gate electrode film over the dielectric film, and modifying a surface layer of the metal-containing gate electrode film by exposing the metal-containing gate electrode film to a process gas containing an oxygen-containing gas, a nitrogen-containing gas, or an oxygen- and nitrogen-containing gas, where a thickness of the modified surface layer is less than a thickness of the metal-containing gate electrode film. The method further includes, heat-treating the modified metal-containing gate electrode film to form a stressed metal-containing gate electrode film that exhibits stress over the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.