Semiconductor memory structure with stress regions
US8008692B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 18, 2008 |
| Grant date | Aug 30, 2011 |
| Priority date | — |
| Expiry date | May 31, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/792
Abstract
A semiconductor memory structure with stress regions includes a substrate defining a first and a second device zone; a first and a second stress region formed in each of the first and second device zone to yield stress different in level; a barrier plug separating the two device zones from each other; and a plurality of oxide spacers being located between the first stress regions and the barrier plug while in direct contact with the first stress regions. Due to the stress yielded at the stress regions, increased carrier mobility and accordingly, increased reading current can be obtained, and only a relatively lower reading voltage is needed to obtain an initially required reading current. As a result, the probability of stress-induced leakage current is reduced to enhance the data retention ability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.