Semiconductor chip package, electronic device including the semiconductor chip package and methods of fabricating the electronic device
US8008771B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2008 |
| Grant date | Aug 30, 2011 |
| Priority date | — |
| Expiry date | Oct 19, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor chip package including a semiconductor chip including a first surface having bonding pads, a second surface facing the first surface, and sidewalls; a molding extension part surrounding the second surface and the sidewalls of the semiconductor chip; redistribution patterns extending from the bonding pads over the molding extension part, and electrically connected to the bonding pads; bump solder balls on the redistribution patterns; and a molding layer configured to cover the first surface of the semiconductor chip and the molding extension part, while exposing portions of each of the bump solder balls. The molding layer has concave meniscus surfaces between the bump solder balls adjacent to each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.