Adaptive clock generators, systems, and methods
US8008961B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2009 |
| Grant date | Aug 30, 2011 |
| Priority date | — |
| Expiry date | Dec 14, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00215
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Adaptive clock generators, systems, and related methods than can be used to generate a clock signal for a functional circuit to avoid or reduce performance margin are disclosed. In certain embodiments, a clock generator autonomously and adaptively generates a clock signal according to a delay path(s) provided in a delay circuit(s) relating to a selected delay path(s) in the functional circuit(s). The clock generator includes a delay circuit(s) adapted to receive an input signal and delay the input signal by an amount relating to a delay path(s) of a functional circuit(s) to produce an output signal. A feedback circuit is coupled to the delay circuit(s) and responsive to the output signal, wherein the feedback circuit is adapted to generate the input signal back to the delay circuit(s) in an oscillation loop configuration. The input signal can be used to provide a clock signal to the functional circuit(s).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.