Latch based optimization during implementation of circuit designs for programmable logic devices
US8010923B1 · kind B1 · utility
3Cited by
8References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 28, 2008 |
| Grant date | Aug 30, 2011 |
| Priority date | — |
| Expiry date | Dec 12, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer-implemented method of implementing a circuit design within a programmable logic device can include selecting at least one circuit element of the circuit design. The selected circuit element can be converted to a latch. A timing analysis can be performed upon the circuit design after conversion of the selected circuit element to a latch. A determination can be made as to whether the timing of the circuit design improves and the conversion of the selected circuit element to a latch can be accepted when the timing of the circuit design improves. The circuit design can be output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.