Mechanism for monitoring instruction set based thread execution on a plurality of instruction sequencers

US8010969B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Richard Hankins · San Jose, US
• Gautham Chinya · Hillsboro, US
• Hong Wang · Santa Clara, US
• Shivnandan Kaushik · Portland, US
• Bryant Bigbee · Scottsdale, US
• John Shen · Tainan, TW
• Trung Diep · San Jose, US
• Xiang Zou · Beaverton, US
• Baiju V. Patel · Portland, US
• Paul M. Petersen · Phoenix, US
• Sanjiv Shah · Champaign, US
• Ryan Rakvic · Palo Alto, US
• Prashant Sethi · Folsom, US

Key dates

• Filing date: Jun 13, 2005
• Grant date: Aug 30, 2011
• Expiry date: Dec 1, 2028

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2201/88
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A technique to monitor software thread performance and update software that issues or uses the thread(s) to reduce performance-inhibiting events. At least one embodiment of the invention uses hardware and/or software timers or counters to monitor various events associated with executing user-level threads and report these events back to a user-level software program, which can use the information to avoid or at least reduce performance-inhibiting events associated with the user-level threads.