Method of manufacturing the double-implant nor flash memory structure
US8012825B2 · kind B2 · utility
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6Claims
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Key dates
| Filing date | Jan 8, 2009 |
| Grant date | Sep 6, 2011 |
| Priority date | — |
| Expiry date | Jan 2, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6891
Abstract
In a method of manufacturing a double-implant NOR flash memory structure, a phosphorus ion implantation process is performed, so that a P-doped drain region is formed in a semiconductor substrate between two gate structures to overlap with a highly-doped drain (HDD) region and a lightly-doped drain (LDD) region. Therefore, the electric connection at a junction between the HDD region and the LDD region is enhanced and the carrier mobility in the memory is not lowered while the problems of short channel effect and punch-through of LDD region are solved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.