ORO and ORPRO with bit line trench to suppress transport program disturb

US8012830B2 · kind B2 · utility

Assignee

• Spansion LLC. · US

Inventors

• Ning Cheng · San Jose, US
• Kuo-Tung Chang · Saratoga, US
• Hiro Kinoshita · San Jose, US
• Chih-Yuh Yang · San Jose, US
• Lei Xue · 红钢城街道, CN
• Chungho Lee · Sunnyvale, US
• Minghao Shen · Road Town, VG
• Angela T. Hui · Fremont, US
• Huaqiang Wu · Nanhu, CN

Key dates

• Filing date: Aug 8, 2007
• Grant date: Sep 6, 2011
• Expiry date: Jan 21, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/037

Abstract

Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line openings containing a bit line dielectric between the memory cells. The memory cell contains a charge storage layer and a first poly gate. The bit line opening extends into the semiconductor substrate. By containing the bit line dielectric in the bit line openings that extend into the semiconductor substrate, the memory device can improve the electrical isolation between memory cells, thereby preventing and/or mitigating TPD.