Patent · US Active

Techniques for integrated circuit clock management using multiple clock generators

US8014485B2 · kind B2 · utility

6Cited by

34References

20Claims

0Family size

Assignee

Advanced Micro Devices, Inc. · US

Inventors

Bill K. C. Kwan · Austin, US
Craig Daniel Eaton · Austin, US
Daniel W. Bailey · Portsmouth, GB

Key dates

Filing date	May 17, 2007
Grant date	Sep 6, 2011
Priority date	—
Expiry date	Nov 30, 2029

Classification

Technology area (CPC H)Electricity
CPC primaryH03L7/06
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A clock generator system (400) includes a phase locked loop (PLL) (402), a first clock generator (404), and a second clock generator (406). The PLL (402) includes a first output configured to provide a first clock signal at a first frequency and a second output configured to provide a second clock signal at the first frequency. The second clock signal is out-of-phase with the first clock signal. An output of the first clock generator (404) is configured to provide a first generated clock signal whose effective frequency is based on both the first and second clock signals and a first mode signal. An output of the second clock generator (406) is configured to provide a second generated clock signal whose effective frequency is based on both the first and second clock signals and a second mode signal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.