Routing of wires of an electronic circuit
US8015527B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 2008 |
| Grant date | Sep 6, 2011 |
| Priority date | — |
| Expiry date | Dec 21, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention relates to a delay calculation method for wiring nets of an electronic circuit, wherein a net within an electronic circuit comprises a driver pin and a receiving pin being coupled by at least one loop, the loop comprising a first branching path and a second branching path electrically parallel to the first branching path, wherein at least a first and a second branching point connect the branching paths. The method comprises the steps of disconnecting each branching path once at a time at a specific point in said the at least one loop which connects a driver to at least one specific receiving pin; calculating a delay value of a signal connection between the driver pin and each of the receiving pin for each of the disconnected branching paths of each loop; storing maximum and/or minimum calculated delay values; and applying at least one of the delay values for static timing analysis of the electronic circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.