Method for manufacturing a semiconductor package
US8017437B2 · kind B2 · utility
41Cited by
2References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 1, 2009 |
| Grant date | Sep 13, 2011 |
| Priority date | — |
| Expiry date | Dec 1, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor package which includes mounting a first chip on a first substrate by a flip chip method, the first substrate having a pre-designed pattern formed thereon; forming at least one bump by performing soldering, on at least one predetermined position electrically connected with the pattern formed on the first substrate; forming a first molding by performing molding, such that the first molding covers the first substrate and the first chip; placing an interposer on the first molding; and placing a second substrate on the interposer, the second substrate having a second chip mounted thereon.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.