Warpage-compensating die paddle design for high thermal-mismatched package construction
US8017445B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 2007 |
| Grant date | Sep 13, 2011 |
| Priority date | — |
| Expiry date | Aug 25, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and packaging for semiconductor devices and integrated circuits is disclosed that eliminates warpage stress on packages caused by coefficient of thermal expansion (CTE) mismatch between the device, lead frame or die paddle and a molding compound. Generally, the method includes steps of: (i) mounting the die on which the device is fabricated to a die paddle of a leadframe; and (ii) encapsulating the die on the die paddle and at least a portion of the leadframe in a molding compound, wherein a difference between a first volume of molding compound above a plane of the leadframe and a second volume of molding compound below the plane of the leadframe is sufficiently reduced to substantially eliminate warpage of the finished package due to mismatch of CTEs of the device, lead frame and packaging compound. The die paddle may be etched or reduced to facilitate molding compound flowing under the plane of the leadframe. Other embodiments are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.