Dual high-k oxides with sige channel

US8017469B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Tien Ying Luo · Austin, US
• Gauri Karve · Cohoes, US
• Daniel G. Tekleab · Wappingers Falls, US

Key dates

• Filing date: Jan 21, 2009
• Grant date: Sep 13, 2011
• Expiry date: Jul 23, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/667

Abstract

A method and apparatus are described for integrating dual gate oxide (DGO) transistor devices (50, 52) and core transistor devices (51, 53) on a single substrate (15) having a silicon germanium channel layer (21) in the PMOS device areas (112, 113), where each DGO transistor device (50, 52) includes a metal gate (25), an upper gate oxide region (60, 84) formed from a second, relatively higher high-k metal oxide layer (24), and a lower gate oxide region (58, 84) formed from a first relatively lower high-k layer (22), and where each core transistor device (51, 53) includes a metal gate (25) and a core gate dielectric layer (72, 98) formed from only the second, relatively higher high-k metal oxide layer (24).