CMOS (complementary metal oxide semiconductor) devices having metal gate NFETs and poly-silicon gate PFETs

US8018005B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Bruce B. Doris · Brewster, US
• William K. Henson · Beacon, US
• Richard S. Wise · Beacon, US
• Hongwen Yan · Somers, US

Key dates

• Filing date: Jun 25, 2010
• Grant date: Sep 13, 2011
• Expiry date: Jun 25, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0177

Abstract

A semiconductor structure. The semiconductor structure includes: a first semiconductor region and a second semiconductor region; a first gate dielectric region on the first semiconductor region; a second gate dielectric region on the second semiconductor region, wherein the second semiconductor region includes a first top surface shared by the second semiconductor region and the second gate dielectric region, and wherein the first top surface defines a reference direction perpendicular to the first top surface and pointing from inside to outside of the second semiconductor region; an electrically conductive layer on the first gate dielectric region; a first poly-silicon region on the electrically conductive layer; a second poly-silicon region on the second gate dielectric region; a first hard mask region on the first poly-silicon region; and a second hard mask region on the second poly-silicon region.