Gate drive voltage boost schemes for memory array
US8018758B2 · kind B2 · utility
3Cited by
6References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 6, 2009 |
| Grant date | Sep 13, 2011 |
| Priority date | — |
| Expiry date | Apr 5, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This invention describes a circuit and method to limit the stress caused by gate voltages required to write a one or zero in magnetic memory elements using the Giant magneto-resistive effect, such as Phase Change RAM and Spin Moment Transfer MRAM, sometimes referred to as Spin Torque Transfer MRAM, which require high programming currents. The circuit and method selects one cell at a time for writing a one or a zero, different voltages to write a one or a zero, and a precharge circuit to limit the stress on non selected cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.