Thin film device fabrication process using 3D template
US8021935B2 · kind B2 · utility
3Cited by
6References
19Claims
0Family size
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Key dates
| Filing date | Oct 1, 2008 |
| Grant date | Sep 20, 2011 |
| Priority date | — |
| Expiry date | Jul 4, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/942
Abstract
A fabrication process for a device such as a backplane for a flat panel display includes depositing thin film layers on a substrate, forming a 3D template overlying the thin film layers, and etching the 3D template and the thin film layers to form gate lines and transistors from the thin film layers. An insulating or passivation layer can then be deposited on the gate lines and the transistors, so that column or data lines can be formed on the insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.