Method of forming CMOS device having gate insulation layers of different type and thickness

US8021942B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Andy Wei · Queensbury, US
• Andrew Waite · Beverly, US
• Martin Trentzsch · Dresden, DE
• Johannes Groschopf · Radebeul, DE
• Gunter Grasshoff · Radebeul, DE
• Andreas Ott · Erfurt, DE

Key dates

• Filing date: Mar 17, 2008
• Grant date: Sep 20, 2011
• Expiry date: Apr 15, 2028

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/926

Abstract

In the process sequence for replacing conventional gate electrode structures by high-k metal gate structures, the number of additional masking steps may be maintained at a low level, for instance by using highly selective etch steps, thereby maintaining a high degree of compatibility with conventional CMOS techniques. Furthermore, the techniques disclosed herein enable compatibility to front-end process techniques and back-end process techniques, thereby allowing the integration of well-established strain-inducing mechanisms in the transistor level as well as in the contact level.